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一、 实验目的和要求
1.熟悉型数字实验箱的结构和使用方法.
2.掌握基本门电路的逻辑功能及测试方法。
二、实验内容和原理
1、数字逻辑实验箱
目前数字电路的实验，通常都在数字逻辑实验箱">
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                <p><strong>实验一</strong>  <strong>数字实验箱的使用及基本门电路的逻辑功能</strong>  </p>
<p><strong>一、</strong> <strong>实验目的和要求</strong></p>
<p>1.熟悉型数字实验箱的结构和使用方法.</p>
<p>2.掌握基本门电路的逻辑功能及测试方法。</p>
<p><strong>二、</strong>实验内容和原理</p>
<p>1、数字逻辑实验箱</p>
<p>目前数字电路的实验，通常都在数字逻辑实验箱上进行，实验箱一般包括以下几个部分组成：</p>
<blockquote>
<p>① 直流稳压电源   ② 脉冲源③ 逻辑电平显示数据电平开关 ④ BCD七段译码显示</p>
<p>⑤ 1C插座及自锁紧插孔       ⑥ 阻容元件区                          ⑦ 电位器组</p>
</blockquote>
<p>2、基本门电路的逻辑功能</p>
<p>常用基本门电路有“与”、“或”、“非”、“与非”、“或非”、“与或非”“异或”。它们的逻辑表达式及逻辑符号为：</p>
<blockquote>
<p>③ 非门<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3CDA.tmp.png">    ①与门Z＝ABCD       ②或门Z＝A+B+C   ④与非门 <img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3CDC.tmp.png"></p>
<p>⑤或非门<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3CDE.tmp.png"> ⑥与非门 <img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3CEF.tmp.png">        ⑦与或非门<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3CF1.tmp.png"></p>
</blockquote>
<p><strong>三</strong>、<strong>操作方法和实验步骤</strong></p>
<p>1、数字逻辑实验箱的使用</p>
<p>(1)将八个电平控制开关(K1K8)的输出插孔与八个电平指示器的输入插孔(L1-L8)依次接通，当开关向上板时，输出高电平即逻辑1，开关向下扳时，输出低电平即逻辑0，板动开关观察电平指示器的L1-L8，使其输出00000000，,11110000，01010101，11111111时，观察电平指示器的指示是否与之相一致。</p>
<p>(2)将电平控制开关K4、K3、K2、K1的输出插孔与BCD码显示器的低位输入端D1、C1、B1、A1依次接通，将电平控制开关K8、K7、K6、K5的输出插孔与BCD码显示器的低位输入端D2、C2、B2、A2依次接通，扳动控制开关其输出为:00000000、00010001、 00100010、00110011、01010101、01100110、10001000、10011001，观察数码管显示的数字，看能否显示0-99的任意数。</p>
<p><strong>四、实验结果与分析</strong></p>
<p>2、基本门电路逻辑功能的测试</p>
<p>(1)或非门逻辑功能的测试</p>
<p>①将或非门74S27插入实验插座上。</p>
<p>②按图2-2接线，门的输入段3、4、5分别接逻辑开关K1、K2、K3的逻辑电平输出插孔，门的输出端6接电平指示器输入端L1，若发光二极管亮表示门的输出状态为“1”，若发光二极管不亮表示门的输出状态为“0”。门的7端接地，14端接+5V。</p>
<p>③使输入端(3、4、5)为表2-1情况下，分别测出输出端(6)的逻辑状态，并将结果填入表2-1中 </p>
<p><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3CF3.tmp.png"> </p>
<table>
<thead>
<tr>
<th>表2-1</th>
<th></th>
<th></th>
<th></th>
</tr>
</thead>
<tbody><tr>
<td>输入</td>
<td>输出</td>
<td></td>
<td></td>
</tr>
<tr>
<td>3(A)</td>
<td>4(B)</td>
<td>5(C)</td>
<td>6(Z)</td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
</tbody></table>
<p>图2-2</p>
<p>(2)与或非门逻辑功能的测试</p>
<p>①将与或非门74LS51插入实验室插座上。按图2-3连接好电路。</p>
<p>②接通电源，按表2-2的要求进行实验。将测得的结果填入表中。</p>
<table>
<thead>
<tr>
<th>表2-2</th>
<th></th>
<th></th>
<th></th>
<th></th>
</tr>
</thead>
<tbody><tr>
<td>输入</td>
<td>输出</td>
<td></td>
<td></td>
<td></td>
</tr>
<tr>
<td>2(A)</td>
<td>3(B)</td>
<td>4(C)</td>
<td>5(D)</td>
<td>6(Z)</td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
</tbody></table>
<p><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3CF4.tmp.png">        </p>
<p>图2-3</p>
<p>(3)异或门逻辑功能的测试</p>
<p>①将异或门74LS86插入实验室插座上。按图2-4连接好电路。</p>
<p>②接通电源，按表2-3的要求进行实验。将测得的结果填入表中。</p>
<table>
<thead>
<tr>
<th>表2-3</th>
<th></th>
<th></th>
</tr>
</thead>
<tbody><tr>
<td>输入</td>
<td>输出</td>
<td></td>
</tr>
<tr>
<td>1(A)</td>
<td>2(B)</td>
<td>3(Z)</td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
</tbody></table>
<p>(4)与非门逻辑功能的测试</p>
<p>①将与非门74LS20插入实验室插座上。按图2-5连接好电路。</p>
<p>②接通电源，按表2-4的要求进行实验。将测得的结果填入表中。</p>
<table>
<thead>
<tr>
<th>表2-4</th>
<th></th>
<th></th>
<th></th>
<th></th>
</tr>
</thead>
<tbody><tr>
<td>输入</td>
<td>输出</td>
<td></td>
<td></td>
<td></td>
</tr>
<tr>
<td>1(A)</td>
<td>2(B)</td>
<td>4(C)</td>
<td>5(D)</td>
<td>6(Z)</td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
</tbody></table>
<p><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3CF6.tmp.png"> </p>
<p>图2-5</p>
<p>(5)利用与非门组成其它逻辑门，并测试其逻辑功能</p>
<p>①非门</p>
<p>74LS20是四输入端双与非门，前面的实验只用了一个与非门，现在将另一个与非门按图2-6接成非门。接通电源，按表2-5的要求进行实验，并将测得的结果填入表中。</p>
<p><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3CF7.tmp.png"> </p>
<table>
<thead>
<tr>
<th>表2-5</th>
<th></th>
</tr>
</thead>
<tbody><tr>
<td>输入</td>
<td>输出</td>
</tr>
<tr>
<td>9(A)</td>
<td>8(Z)</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
</tr>
</tbody></table>
<p>图2-6</p>
<p>分析：通过芯片的内部结构来了解掌握芯片的功能以及使用方法；在连接线路以及安装芯片时不要忘了关闭电源；安装芯片时注意芯片不要安反以防烧毁芯片；开始实验前要检查线路以及指示灯能否正常工作；</p>
<p><strong>实验 二 组合电路的实验分析</strong>    </p>
<p><strong>一、实验目的</strong></p>
<ol>
<li><p>掌握组合电路的分析方法</p>
</li>
<li><p>验证半加器、全加器的逻辑功能</p>
</li>
</ol>
<p><strong>二、实验内容</strong></p>
<p>1、半加器逻辑功能测试</p>
<p>2、全加器逻辑功能的测试</p>
<p>3、四位二进制全加器逻辑功能的测试</p>
<p>一、 操作方法和实验步骤</p>
<p>（一）、半加器逻辑功能测试</p>
<p>   实验步骤</p>
<ol>
<li>写出S与C的逻辑表达式</li>
</ol>
<blockquote>
<p>S=A <code>·</code> B+ <code>A B</code> `; </p>
<p>C=AB`</p>
</blockquote>
<ol start="2">
<li>做出逻辑电路连接图。</li>
</ol>
<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3CF8.tmp.png" style="zoom: 50%;" /> 

<ol start="3">
<li>链接电路，并验证实验结果。</li>
</ol>
<table>
<thead>
<tr>
<th>输入</th>
<th>输出</th>
<th></th>
<th></th>
</tr>
</thead>
<tbody><tr>
<td>A</td>
<td>B</td>
<td>S</td>
<td>C</td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>0</td>
<td>1</td>
</tr>
</tbody></table>
<p>（二）、全加器逻辑功能的测试</p>
<p>实验步骤</p>
<ol>
<li><p>写出Sn与Cn的逻辑表达式</p>
</li>
<li><p>链接电路</p>
</li>
<li><p>链接电路并验证实验结果。</p>
</li>
</ol>
<table>
<thead>
<tr>
<th>输入</th>
<th>输出</th>
<th></th>
<th></th>
<th></th>
</tr>
</thead>
<tbody><tr>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3CF9.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D09.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D0A.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D0B.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D0C.tmp.png"></td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
</tbody></table>
<p>（三）、 四位二进制全加器逻辑功能的测试</p>
<ol>
<li>链接电路并验证实验结果。</li>
</ol>
<table>
<thead>
<tr>
<th>输入</th>
<th>输出</th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
</tr>
</thead>
<tbody><tr>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D0D.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D0E.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D0F.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D10.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D11.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D12.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D13.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D14.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D15.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D16.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D17.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D18.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D19.tmp.png"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D1A.tmp.png"></td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
</tr>
</tbody></table>
<p><strong>三、实验结果与分析</strong></p>
<p>实验结果：完成了三个实验任务，对半加器，全加器，和74LS83芯片的设计和功能有更深刻的了解。</p>
<p>分析： 半加器只能够实现同一位上的两个数的相加，可以通过异或和与非门实现，全加器能够计算来自前一位的进位，集成的74LS83芯片可以通过级联应用实现连续多位的运算。</p>
<p><strong>实验  三 组合逻辑电路的设计（一）</strong>     </p>
<p><strong>一、实验目的</strong></p>
<p>掌握组合逻辑电路的设计方法，并通过实验结果验证理论知识。</p>
<p><strong>二、实验内容与步骤</strong></p>
<p>1、设计一个半减器，使之能完成两个一位二进制数<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D2B.tmp.png" alt="img">和<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D2C.tmp.png" alt="img">的减法运算（不考虑低位的借位），输出差和向高位的借位。</p>
<p>2、设计一个表决电路，三个输入<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D2D.tmp.png" alt="img">有两个或两个以上为1时，输出为1，否则输出为0。</p>
<p><strong>三、 实验结果</strong></p>
<blockquote>
<p>1、详细写明整个实验过程</p>
<p>2、将实验过程和实验结果叙述清楚。</p>
</blockquote>
<p>实验一：</p>
<p>真值表</p>
<table>
<thead>
<tr>
<th>A</th>
<th>B</th>
<th>Di</th>
<th>Bo</th>
</tr>
</thead>
<tbody><tr>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
</tr>
</tbody></table>
<p>实验二:</p>
<p>电路图：</p>
<p> 真值表</p>
<table>
<thead>
<tr>
<th>A</th>
<th>B</th>
<th>C</th>
<th>S</th>
</tr>
</thead>
<tbody><tr>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
</tbody></table>
<p><strong>实验  四  74LS138芯片的测试及应用</strong>    </p>
<p>一 、 实验目的</p>
<p>1掌握组合逻辑电路的相关知识</p>
<p>2 学会使用操作74LS138芯片。</p>
<p>二 、 实验内容</p>
<p>1.测试74LS138芯片的功能。</p>
<p>2.使用74LS138译码器实训F=AB+BC+AC</p>
<p>三 、 操作方法与实验步骤</p>
<p>1.根据引脚图，对芯片进行连线，得到真值表</p>
<p><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D30.tmp.png"> </p>
<ol start="2">
<li>验证真值表</li>
</ol>
<table>
<thead>
<tr>
<th>输入</th>
<th>输出</th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
</tr>
</thead>
<tbody><tr>
<td>S1</td>
<td>S2<code>+S3</code></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D31.tmp.png" alt="img"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D32.tmp.png"></td>
<td>A0</td>
<td>Y0`</td>
<td>Y1`</td>
<td>Y2`</td>
<td>Y3`</td>
<td>Y4`</td>
<td>Y5`</td>
<td>Y6`</td>
<td>Y7`</td>
</tr>
<tr>
<td>0</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>X</td>
<td>1</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
</tbody></table>
<p>3.<code> 将与或式化为与非与非式：</code></p>
<p>AB+BC+AC=ABC+ABC<code>+A</code>BC+AB<code>·</code>C=((ABC)’(ABC’)(A<code>·</code>BC)(AB`C))’</p>
<ol start="4">
<li><code>根据与非与非式设计电路。</code></li>
</ol>
<p><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D33.tmp.jpg"> </p>
<p>四． 实验结果及分析</p>
<p>当一个选通端为高电平，另两个选通端和为低电平时，可将地址端的二进制编码在Y0至Y7对应的输出端以低电平译出。</p>
<p>任何时刻要么全为高电平1—芯片处于不工作状态，要么只有一个为低电平0，其余7个输出全为高电平1。</p>
<p>使用74LS138译码器进行编程即将要求的内容转化成74LS138芯片对应的输出的形式</p>
<p><strong>实验五 触发器</strong> </p>
<p>一 实验目的</p>
<p>1、学习触发器逻辑功能的测试方法</p>
<p>2、学习基本RS触发器，JK触发器，D触发器的逻辑功能及触发方式。</p>
<p>3、了解不同触发器之间的相互转换。</p>
<p>二 实验内容与步骤</p>
<p>1、D触发器逻辑功能测试</p>
<p>(1)用一块集成D触发器74LLS74，按图6-6接线，<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D34.tmp.jpg">、<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D45.tmp.jpg">、D端分别接电平控制开关插孔K1、K2、K3，CP端接单脉冲输出插孔P+， Q、<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D46.tmp.jpg" alt="img">端分别接电平指示器插孔L1、L2。</p>
<p>(2)直接置0、置1功能测试</p>
<p>按表6-2的要求，改变<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D47.tmp.jpg" alt="img">、<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D48.tmp.jpg" alt="img"> (D和CP处于任意状态)，测试<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D49.tmp.jpg" alt="img">、<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D4A.tmp.jpg">的功能，并将测试结果填入表6-2中。</p>
<p>(3)逻辑功能测试</p>
<p>将<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D4B.tmp.jpg" alt="img">和端置1，按表6-3的要求进行实验，并将测试结果填入表中。</p>
<p><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D4D.tmp.png"></p>
<p>图6-6</p>
<p>3、JK触发器逻辑功能测试</p>
<p>(1)用一块集成JK触发器74LLS76, 按图6-7接线，<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D4E.tmp.jpg">、<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D4F.tmp.jpg">、J、K端分别接电平控制开关插孔K1、K2、K3、K4，CP端接单脉冲输出插孔P+，Q、<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D50.tmp.jpg">端分别接电平指示器插孔L1、L2。</p>
<p>(2)直接置0、置1功能测试</p>
<p>按表6-4的要求，改变<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D51.tmp.jpg">、<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D52.tmp.jpg" alt="img" style="zoom: 80%;" /> (J、K和CP处于任意状态)，测试<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D53.tmp.jpg">、<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D54.tmp.jpg">的功能，并将测试结果填入表中。 </p>
<p> (3).逻辑功能测试</p>
<p>将<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D55.tmp.jpg" alt="img">和端置1，按表6-5的要求进行实验，并将测试结果填入表中。</p>
<p><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D66.tmp.png"></p>
<p>图6-7</p>
<p>(1)将JK触发器转换成T触发器，验证其逻辑功能。</p>
<p>(2)将D触发器转换成将JK触发器转换成<img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D67.tmp.jpg" alt="img">触发器，验证其逻辑功能。从CP端输入3.5V的连续脉冲，用双踪示波器观察并画出触发器的输入输出波形。</p>
<p>以下两项为选作内容：</p>
<p>(3)将D触发器转换成JK触发器，验证其逻辑功能。</p>
<p>(4)将JK触发器转换成D触发器，验证其逻辑功能。</p>
<p>三 实验结果</p>
<p>表6-2</p>
<table>
<thead>
<tr>
<th><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D68.tmp.jpg"></th>
<th><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D69.tmp.jpg"></th>
<th>Q</th>
<th>Q’</th>
</tr>
</thead>
<tbody><tr>
<td>0➡1</td>
<td>0</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1➡0</td>
<td>0</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>0</td>
<td>0➡1</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>1➡0</td>
<td>1</td>
<td>1</td>
</tr>
</tbody></table>
<p>表6-3</p>
<table>
<thead>
<tr>
<th>D</th>
<th>CP</th>
<th>Q</th>
<th></th>
</tr>
</thead>
<tbody><tr>
<td>Q=0</td>
<td>Q=1</td>
<td></td>
<td></td>
</tr>
<tr>
<td>0</td>
<td>⬆</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>⬇</td>
<td>0</td>
<td>1</td>
<td></td>
</tr>
<tr>
<td>1</td>
<td>⬆</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>⬇</td>
<td>1</td>
<td>1</td>
<td></td>
</tr>
</tbody></table>
<p>表6-4</p>
<table>
<thead>
<tr>
<th><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D6A.tmp.jpg"></th>
<th><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D6B.tmp.jpg"></th>
<th>Q</th>
<th>Q’</th>
</tr>
</thead>
<tbody><tr>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
</tr>
</tbody></table>
<p>表6-5</p>
<table>
<thead>
<tr>
<th>J</th>
<th>K</th>
<th>CP</th>
<th><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D6C.tmp.jpg"></th>
<th></th>
</tr>
</thead>
<tbody><tr>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D6D.tmp.jpg" alt="img"></td>
<td><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D6E.tmp.jpg" alt="img"></td>
<td></td>
<td></td>
<td></td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>↓</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>↓</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>↓</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>↓</td>
<td>1</td>
<td>0</td>
</tr>
</tbody></table>
<p><strong>实验六：计数器（一）</strong>    </p>
<p>一 、实验目的</p>
<p>1、学习用JK触发器组成计数器。</p>
<p>2、学习计数器逻辑功能的测试方法。</p>
<p>3、熟悉异步二进制计数器，异步二一十进制计数器的工作原理。</p>
<p>二 、实验内容及原理</p>
<p>1.异步二进制计数器</p>
<p><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D6F.tmp.png">真值表：</p>
<table>
<thead>
<tr>
<th>CP数</th>
<th>二进制码</th>
<th>十进制数</th>
<th></th>
<th></th>
<th></th>
</tr>
</thead>
<tbody><tr>
<td>Q4</td>
<td>Q3</td>
<td>Q2</td>
<td>Q1</td>
<td></td>
<td></td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>2</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>2</td>
</tr>
<tr>
<td>3</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>3</td>
</tr>
<tr>
<td>4</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>4</td>
</tr>
<tr>
<td>5</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>5</td>
</tr>
<tr>
<td>6</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>6</td>
</tr>
<tr>
<td>7</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>7</td>
</tr>
<tr>
<td>8</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>8</td>
</tr>
<tr>
<td>9</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>9</td>
</tr>
<tr>
<td>10</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>10</td>
</tr>
<tr>
<td>11</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>11</td>
</tr>
<tr>
<td>12</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>12</td>
</tr>
<tr>
<td>13</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>13</td>
</tr>
<tr>
<td>14</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>14</td>
</tr>
<tr>
<td>15</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>15</td>
</tr>
<tr>
<td>16</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
</tbody></table>
<p>2、异步二一十进制计数器</p>
<p><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D70.tmp.png"> </p>
<p>验证真值表：</p>
<table>
<thead>
<tr>
<th>CP数</th>
<th>二进制码</th>
<th>十进制数</th>
<th>进位C</th>
<th></th>
<th></th>
<th></th>
</tr>
</thead>
<tbody><tr>
<td>Q4</td>
<td>Q3</td>
<td>Q2</td>
<td>Q1</td>
<td></td>
<td></td>
<td></td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>2</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>2</td>
<td>0</td>
</tr>
<tr>
<td>3</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>3</td>
<td>0</td>
</tr>
<tr>
<td>4</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>4</td>
<td>0</td>
</tr>
<tr>
<td>5</td>
<td>0</td>
<td>1</td>
<td>0</td>
<td>1</td>
<td>5</td>
<td>0</td>
</tr>
<tr>
<td>6</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>0</td>
<td>6</td>
<td>0</td>
</tr>
<tr>
<td>7</td>
<td>0</td>
<td>1</td>
<td>1</td>
<td>1</td>
<td>7</td>
<td>0</td>
</tr>
<tr>
<td>8</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>8</td>
<td>0</td>
</tr>
<tr>
<td>9</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>1</td>
<td>9</td>
<td>1</td>
</tr>
<tr>
<td>10</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
</tbody></table>
<p>三 、操作方法与实验步骤</p>
<p>1.由实验讲义，我们已知异步二进制计数器和同步二进制计数器的逻辑图和74LS73芯片的引脚图。</p>
<p>2.测试足够数量的接线，并分别测试芯片的功能，保证实验的正常进行。</p>
<p>3.参照引脚图 我们可以进行连线，并进行测试。</p>
<p>四 、实验结果及分析</p>
<p>1 在异步的二进制计数器中,Q1随每一个下降沿的出现而反转，Q2,Q3,Q4依次是根据上一个输出端的下降沿出现而反转，Q1,Q2,Q3,Q4的反转频率依次是上一级的一半。</p>
<p>2 相较于异步的二进制计数器，异步的二-十进制计数器，多了由输出信号向输入信号的负反馈，通过负反馈，完成，每十个脉冲一组的循环。通过这种负反馈我们可以类似的作出其他进制的计数器。</p>
<p><strong>实验七  触发器逻辑功能的测试</strong> </p>
<p><strong>一、实验目的和要求</strong></p>
<p>实验一：测试两个74LS160芯片和与非门74LS00芯片组成的100进制计数器的功能；</p>
<p>实验二：测试两个74LS160芯片和与非门74LS00芯片外加74LS20芯片组成的27进制计数器的功能；</p>
<p><strong>二、 实验内容和原理</strong></p>
<p><strong>原理：</strong></p>
<p>74LS160是集成单元二一十进制同步计数器，它除计数外，还有全复0，状态预置，保持等功能。</p>
<p>计数器74LS160的CP为计数脉冲输入端; Cr是复位控制端，当Cr为低电平时，不管其它输入信号如何，计数器立即恢复到0000状态，LD为状态预置控制端。当Cr=1, LD=0, 且CP端输入一个上升沿时，将使输入的A、B、C、D状态预置到计数器的状态QA, QB, Qc, QD上去了，P和T都是保持控制端，当Cr=LD=1,.而P或T为0时，不管有无CP信号及ABCD如何，计数器将保持原状态不变，只有当Cr、LD、P、T四个控制端全为高电平1时，计数器才能按8421码计数，而且状态是在CP上升沿时翻转。此外还有进位输出端Oc;它的作用是每计数至1001时，输出一个宽度等于计数脉冲周期的正脉冲信号。</p>
<p>两个十进制计数器可以组成一个10X 10-100进制的计数器，个位计数器的进位输出端Oc就作为十位计数器的CP输入，当个位计数器从0开始输入十个计数脉冲时，其Oc端输出一个下降沿，经G倒相，就成为十位计数器翻转所需要的上升沿。</p>
<p>在100进制计数器的基础上，加上一定的复位反馈电路，可以构成100以内的任意进制计数器。本实验要求构成27进制计数器，也就是当十位计数器状态成为0010, 个位计数器状态成为0111时，产生一个复位信号，使两位计数器为状态返回到0000状态。当计数到27时，QA、QB、QC、QB均为1，与非门G输出为0，使两位计数器复位。</p>
<p><strong>内容：</strong></p>
<p>1、74LS160芯片组成100进制计数器的功能测试</p>
<p>2、74LS160芯片组成27进制计数器的功能测试</p>
<p><strong>三、 操作方法与实现步骤</strong></p>
<p>1、74LS160芯片组成100进制计数器的功能测试</p>
<p>(1)由两块十进制计数器74LS160和一块双与非门74LS00 按图2连接可组成100进制计数器。这里使QA，QB, QC， QD接BCD码输入端的高四位，QA，QB, QC， QD接BCD码输入端的低四位。由实验箱的数码管来显示计数器的状态。首先使两个计数器都清零，然后计数。观察显示数字的变化规律。看其是否是100进制计数器。</p>
<p><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D81.tmp.png"></p>
<p>图2</p>
<p>注意图2左侧的芯片从15输出端引出导线连接与非门74LS00后再与右侧芯片的接口2相连，测试时建议选择最低的频率以便于观察。</p>
<p>2、74LS160芯片组成27进制计数器的功能测试</p>
<p>(1)在100进制计数器的基础上，按图3增加与非门G的有关连线(G由74LS20担任)，即可组成27进制计数器。首先清零，然后计数，观察显示数字的变化规律。看其是否是27进制计数器。</p>
<p><img src="https://shierjinghuang.github.io/2021/10/05/%E6%95%B0%E5%AD%97%E7%94%B5%E8%B7%AF%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/wps3D82.tmp.png"></p>
<p>图3</p>
<p>(2)注意连接的导线从74LS20芯片中输出后要返回到两个74LS160芯片的输入端cp段（接口为2），然后连接到脉冲后选择最低频率观察。</p>
<p><strong>四、 实验结果与分析</strong></p>
<p>1、74LS160芯片组成100进制计数器的功能测试</p>
<p>观察到数码显示器能成功地从1跳到99即可。</p>
<p>分析：要接成100进制加法计数器, 重点在于处理低位74160从1001-&gt;0000时向高位74160提供进位信号的问题.当低位74160到达状态1001后, 其RCO引脚变为高电平; 此时高位74160的ENT引脚也随之变为高电平. 当下一系统上升沿信号到来时, 两片74160的状态都+1, 而后低位74160的状态变为0000, 其RCO引脚随之变为低电平, 高位74160的ENT引脚也随之变为低电平. 当系统上升沿信号再次到来时, 低位74160依旧实现+1操作, 而高位74160由于其ENT引脚变为低电平, 则处于保持状态: 直到低位74160的状态再次到达1001时, 再次重复上述过程 </p>
<p>2、74LS160芯片组成27进制计数器的功能测试</p>
<p>观察到数码显示器能成功地从1跳到26即可。</p>
<p>分析：要接成27进制加法计数器, 重点在于处理低位74160从1001-&gt;0000时向高位74160提供进位信号的问题.通过在第一片外加的逻辑电路，每计数到7会译出一个信号与上第二片的外加逻辑电路每到2译出的信号，此信号就是计数到27的进位信号，将此信号再接回两片的清零或置数端即可。</p>
<p><strong>五、实验反思</strong></p>
<p>由于我们拿到的芯片并非是正确的74LS160芯片，而是标上74LS160芯片的161芯片，我们的实验无法正常进行实际上得到的是256位计数器，同样在设计27进制计数器时按照接线图链接的结果也不是27进制。</p>

                
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